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Jobs/Graphic Designer Role/K2 Space - Senior ASIC Physical Design Engineer
K2 Space

K2 Space - Senior ASIC Physical Design Engineer

Remote - United States$170k - $250k+ Equity3w ago
RemoteSeniorNASemiconductorsGraphic DesignerProduct DesignerVendor ManagementFront-endDocumentation

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Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. • 5–10 years of experience in ASIC physical design for complex SoCs. • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). • Strong understanding of timing analysis, power optimization, and physical verification flows. • Experience with hierarchical or flat SoC design methodologies. • Familiarity with FinFET technologies. • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. • Exposure to radiation-hardened or space-qualified ASICs. • Experience with chip-package co-design or advanced packaging (2.5D/3D). • Familiarity with physical design service vendor management or offshore collaboration. • Experience with sign-off through TSMC. • Experience with Gate-All-Around technologies. • Experience working in cross-functional, geographically distributed teams.

Responsibilities

• Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. • Perform timing closure and optimization across multiple corners and modes using industry-standard tools. • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. • Develop and maintain scripts and automation to improve flow efficiency and consistency. • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. • Assist in chip-level integration, ECOs, and tapeout preparation. • Contribute to methodology development, tool evaluation, and flow documentation. • Support your product through production and spaceflight.

Benefits

• Base salary range for this role is $170,000 – $250,000 + equity in the company • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks • If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! • If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. • Export Compliance • Export Compliance • As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” • The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. • Equal Opportunity • Equal Opportunity

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