Axelera AI - Senior/Staff DFT Engineer

• Experience: minimum of 5 years in DFT engineering, preferably with complex SoC projects. • Skills: SystemVerilog RTL, TCL, Python, Unix/Linux workflows. • Core Knowledge: Hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, gate-level verification. • Tools: Siemens, Synopsys, or Cadence DFT tool experience. • Bonus: Familiarity with IEEE 1149.x / 1500 / 1687 standards, synthesis flow, timing analysis. • Strong problem-solving skills, collaboration, and passion for semiconductor innovation. • We offer a flexible working arrangement, with options to: • Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom) if you're already based in the vicinity. • Work fully remotely from any European country (incl. the UK) you are already in. • Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven). • Kindly note that priority will be given to candidates who are [interested in being] based in Belgium or Italy. • This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares. • An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team. • At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.