Delos Data Inc - DFT Engineer
Requirements
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field • 5+ years of experience in digital design verification, with at least 2 in DFT verification specifically • Strong hands-on experience with UVM-based or similar verification methodologies • Proficiency in SystemVerilog • Experience in scripting (preferably Python) and automation • Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium) • Experience with industry-standard EDA DFT tools (e.g., Synopsys TestMax + Yield Accelerator, Siemens Tessent) • Solid understanding of digital design fundamentals • Experience with verification of test sequences for high-speed PHY logic including PCIe and Ethernet (10G/40G/100G) • Strong analytical and problem-solving skills • Clear written and verbal communication skills for cross-functional collaboration • High attention to detail and ability to deliver reliable, high-quality verification outcomes • Ability to work independently and manage tasks to completion • Experience with change control systems, especially git • Experience verifying SoC-level designs
Responsibilities
• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies • Create and execute coverage-driven verification plans aligned with design specifications • Use EDA DFT tools (e.g., TestMax, Tessent) to create and run recommended pre-silicon test cases for MBIST and scan fabric inserted by those tools • Develop directed test cases for other (non-vendor-supplied) DFT logic to validate functionality and identify corner cases • Assist in verifying ATPG patterns, especially at SOC level, along with manufacturing reset sequences • Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with DFT design engineers • Implement and track functional and code coverage, driving verification to closure • Develop reusable verification components and write SystemVerilog Assertions (SVA) • Participate in design and verification reviews, providing input on design testability, correctness, and optimization • Automate regression testing and enhance verification infrastructure using Python and scripting • Contribute to continuous improvement of verification processes, tools, and methodologies • Along with the DFT designers, help support post-silicon test bring-up debug
Benefits
• Target base salary for this role is $160,000 – $230,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.
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