Lumai - AI System Architect
Requirements
• Must-Have • Deep, hands-on understanding of modern AI/ML workloads — transformer architectures, convolutional networks, recommendation systems, or similar — including their compute and memory access patterns • Proven experience defining system or chip architecture in the context of AI/ML acceleration (inference, training, or both) • Ability to build and use analytical performance models (roofline models, memory bandwidth analysis, cycle-accurate estimates) to guide architectural decisions • Strong communication skills with the ability to adapt technical depth for leadership, hardware engineers, and software engineers alike • Experience working across hardware and software boundaries — comfortable discussing ISA design, compiler interfaces, and runtime scheduling as well as datapath microarchitecture • Suitable University education and/or practical experience • Strong Preference For • Experience at an AI chip startup, AI hardware team at a major tech company (e.g. Google TPU, Meta MTIA, AWS Trainium/Inferentia, Tesla Dojo), or a leading fabless semiconductor company • Familiarity with AI compiler stacks (MLIR, XLA, TVM, Triton) and how they interact with hardware architecture decisions • Understanding of chip development processes: RTL design, physical design constraints, and post-silicon bring-up • Experience with or exposure to on-device / edge inference as well as datacenter-scale deployments • Track record of influencing architectural direction through written specs and data-driven arguments rather than authority alone • What Success Looks Like • In your first 90 days, you will have audited the current architectural approach against a defined set of target AI workloads, identified the top architectural risks to schedule and performance, and established a working rhythm with the HW and SW leads. Within six months, you will be the person who others come to when a cross-team decision needs an owner — and the one who keeps the architecture honest against the AI workloads we are building for.
Responsibilities
• Architecture & Technical Leadership • Define and own the end-to-end system architecture, from AI workload characterisation through to chip microarchitecture trade-offs and software stack interfaces • Drive architectural decisions by starting with AI model and operator analysis — identifying compute, memory bandwidth, data movement, and sparsity patterns that constrain and shape the hardware design • Develop and maintain architectural specifications, performance models, and design documents that serve as the single source of truth across teams • Evaluate architectural trade-offs (latency vs. throughput, on-chip vs. off-chip memory, dataflow strategies, precision formats) with a quantitative, workload-grounded methodology • Stay current with the frontier of AI research (model architectures, training techniques, inference optimisations) and translate emerging trends into architectural foresight • Cross-functional Coordination • Act as the primary technical bridge between the leadership team, hardware engineering, and software engineering — ensuring that decisions made in one domain are properly communicated, challenged, and integrated in others • Partner with the leadership team to translate business goals and product roadmap into architectural requirements and phased execution plans • Work closely with the hardware team to ensure microarchitectural decisions are grounded in realistic AI workload demands; push back constructively when hardware-centric thinking diverges from AI requirements • Collaborate with the software team to define clean hardware/software interfaces, programming models, and runtime abstractions that make the hardware genuinely usable for AI practitioners • Facilitate architectural reviews and design discussions that create shared understanding rather than siloed decision-making • Execution & Delivery • Identify and resolve cross-team dependencies and ambiguities early, before they become schedule risks • Define and track key architectural metrics and milestones throughout the chip development lifecycle (pre-RTL through tape-out and post-silicon validation) • Support benchmarking and performance analysis efforts, helping teams understand where the system delivers against AI workload targets and where it falls short
Benefits
• Highly Competitive Salary: We are not saying our salary is a blank check, but let's just say it won't be a source of your stress • Pension Scheme: Plan for retirement with AVIVA • Pension Scheme: • Private Health Insurance: We firmly believe that you come first, and a happy you is a healthy you! Look after yourself and your loved ones with AXA • Private Health Insurance: • Cycle to Work: Spread the cost of a bike, a bike and accessories or just accessories and save on tax • Cycle to Work: • L&D Allowance: Stay at the forefront of your field with a £500 annual development budget • L&D Allowance: • Subsidised On-site Lunches: Enjoy on-site healthy meals at half the price, as Lumai covers 50% of the cost • Subsidised On-site Lunches: • Holidays: Enjoy some deserved "me time" with 25 days paid holiday (plus bank holidays) per year • Holidays:
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