• Partner with analog designers on chip-level and block-level floorplanning and layout strategy
• Drive layout architecture decisions to balance performance, matching, area, and reliability trade-offs
• Execute transistor-level analog IC layout, including critical matching, shielding, and parasitic-sensitive structures
• Lead layout for complex blocks and closely supervise or review layout work from other layout engineers
• Conduct layout design reviews and resolve action items generated as a result of these reviews
• Attend circuit design reviews to provide layout feasibility input and guidance to designers and other layout engineers
• Work with analog and digital designers to ensure layout meets circuit intent and interface requirements
• Own parasitic extraction, LVS, DRC, antenna, and fill closure for assigned blocks and top-level integration
• Support prototype chip bring-up and testing to help validate analog circuit blocks against layout-dependent effects
• Support development of manufacturing test plans where layout impacts testability (e.g., probe access, trim structures)
• Support Product Engineering to meet manufacturing/production needs related to layout and yield
• Support Applications Engineering on layout-related customer questions (e.g., matching, noise, reliability)