Lumai - ASIC Tech Lead (Analog)
Requirements
• Must-Have • 8+ years of hands-on analog or mixed-signal ASIC design experience, with at least one tapeout in a production-intent or high-volume context as the lead designer on one or more critical blocks • Deep expertise in one or more of: TIA/VGA design for optical receivers, high-speed ADC/DAC architectures (SAR, pipeline, sigma-delta), PLL/clock generation, or precision analog (bandgap, LDO, bias) • Strong command of full-custom design flow: schematic, transistor-level simulation (Spectre or similar), post-layout extraction, and statistical/Monte Carlo sign-off • Hands-on silicon bring-up and characterisation experience — comfortable at a bench with an oscilloscope, VNA, signal analyser, and custom test fixtures • Working knowledge of advanced CMOS process nodes (28nm and below, including FD-SOI or FinFET); familiarity with device physics and its practical impact on analog performance • Experience with physical design constraints for analog: matching strategies, layout-dependent effects, shielding, electromigration, and ESD structures • Ability to communicate across disciplines — translating analog constraints and trade-offs clearly for digital designers, firmware engineers, and product stakeholders • MSc or PhD in Electrical Engineering, Microelectronics, or a closely related field; or equivalent demonstrated expertise through industry track record • Strong Preference For • Experience with GlobalFoundries 22FDX (22nm FD-SOI) or comparable RF/analog-optimised process nodes, including body-bias techniques for low-power or high-performance tuning • Background in analog front-ends for photonic or optical systems — coherent or direct-detect receiver design, silicon photonics integration, or lidar/sensing front-ends • Familiarity with mixed-signal design challenges in AI inference hardware: high-throughput data conversion, in-memory compute interfaces, or neuromorphic circuit concepts • Experience with RFIC or mmWave design, particularly high-frequency parasitics management and EM simulation (Momentum, EMX, Sonnet) • Prior experience at a fabless startup or research spin-out from the first tapeout through to product qualification • Contributions to published research or patents in analog/mixed-signal IC design • Familiarity with Python-based characterisation and data analysis workflows for silicon validation (e.g. bench automation, corner sweeps, yield analysis)
Responsibilities
• Architect and own Lumai’s analog and mixed-signal subsystems, including TIA front-ends, VGAs, high-speed ADCs/DACs, PLLs, LDOs, bandgap references, and on-chip bias/calibration circuits • Lead circuit design from concept through full custom schematic capture, pre- and post-layout simulation, and sign-off — taking personal ownership of critical blocks • Define and enforce analog design methodologies, simulation corner strategies, and layout guidelines (matching, shielding, guard rings, substrate noise isolation) across the team • Drive the analog/mixed-signal portions of tapeout: own the sign-off checklist, review LVS/DRC results, and coordinate with the digital and layout teams to meet tape-out milestones • Lead silicon bring-up and characterisation of analog blocks — define bench test plans, debug first-silicon issues, and close the loop between measured silicon behaviour and simulation models • Collaborate with the photonics team to define electrical interfaces to photonic devices (photodetectors, modulators) and co-optimise for noise, bandwidth, and power • Work with the digital ASIC and firmware teams to specify ADC/DAC interfaces, calibration sequences, and real-time closed-loop control requirements • Evaluate and manage the EDA toolchain for analog design (Cadence Virtuoso, Spectre, Calibre, etc.) and maintain or extend the PDK/IP library • Mentor and technically grow junior and mid-level analog designers; conduct design reviews and set the bar for simulation rigour and documentation quality • Engage directly with GlobalFoundries (or other foundry partners) on PDK questions, process corners, and device modelling queries related to 22FDX or equivalent process nodes
Benefits
• You'll work on a new kind of computer. Optical computing for AI has been promised for decades. We have a working system running real models, and the hard part left is taking it to volume. • Your work ships. We are moving from first product to volume production, so what you build this year goes into the servers our customers run. • You'll work across disciplines. Optical engineers, machine learning researchers, and hardware and software engineers solve problems together. You will learn things that don't appear on your job description. • The work matters beyond Lumai. AI's appetite for energy is one of the defining constraints of the next decade. Our mission is sustainable intelligence at global scale: AI that is faster, cheaper to run and far less power-hungry. • You'll join early. You'll have a real say in how we build the product, the team and the way we work. • Equal Opportunity
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