• A degree (BEng, MEng, MSc or equivalent) in Electronic Engineering, Computer Engineering, Computer Science, or a related field — or equivalent practical experience.
• A solid foundational understanding of SoC or computer architecture, including memory hierarchies, on-chip interconnects, and how compute, memory and I/O blocks integrate into a coherent chip, gained through study, projects, internships, or research.
• Some exposure to RTL design concepts and how physical design constraints feed back into architectural choices — academic or internship-level experience is fine.
• Any hands-on exposure to architectural performance modelling tools (gem5, SystemC, or custom cycle-accurate simulators), interconnect/NoC design, compiler/toolchain interactions, or AI acceleration/vector-matrix compute, through study or projects, is highly valued.
• A clear communicator, comfortable working across architecture, modelling, implementation, verification, and software teams, who thrives in ambiguity and fast iteration.