$fractile$

fractile - Semiconductor Product Engineer

London - JJ Mack+ Equity2d ago

In Office Senior EMEA Semiconductors Manufacturing Product Designer Close Documentation

Requirements

• 5+ years of hands-on semiconductor test engineering experience. • Experience developing ATE test programs (Advantest 93K, Teradyne, or similar). • Solid understanding of DFT methodologies (scan, ATPG, MBIST, LBIST) and memory test techniques. • Experience debugging silicon issues and correlating failures to design or process causes. • Familiarity with advanced CMOS nodes and production test challenges. • Ability to work effectively in a cross-functional engineering environment. • Experience testing AI accelerators, GPUs, networking ASICs, or other high-performance compute ICs. • Experience with PCIe Gen5/Gen6, LPDDR4/5/6, or other high-speed interfaces. • Exposure to advanced packaging, chiplets, or multi-die test flows. • Experience improving yield, reducing test time, or optimizing cost in high-volume manufacturing. • Ownership and execution: you will have full agency to drive your work forward • Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines • Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact • Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there • Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

Responsibilities

• Define and develop test methods and strategies for an AI accelerator chip targeting high-volume manufacturing. • Plan and manage manufacturing test content for advanced CMOS designs including high-speed logic, SRAM, DRAM, and high speed IO blocks. • Develop and debug structural and functional test content such as scan/ATPG, LBIST, MBIST, JTAG, and HSIO tests. • Bring up first silicon on ATE, including pattern debug, tester correlation, shmooing, and corner analysis. • Support testing of high-speed interfaces such as PCIe Gen6 and multi-GHz LPDDR, including at-speed tests and margining features. • Execute silicon characterization and failure analysis to identify yield limiters and defect mechanisms. • Optimize test coverage, test time, and cost while maintaining manufacturing robustness. • Work with DFT and design teams to improve testability and close coverage gaps. • Collaborate with OSATs and external partners on test program deployment. • Support advanced packaging test flows, including die-to-die interconnect testing and package-level thermal considerations. • Contribute to documentation of test programs, debug procedures, and manufacturing release materials. • Support qualification, reliability testing, and high-volume manufacturing ramp.

Benefits

• Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role. • Equity & Ownership: meaningful equity so everyone shares in the value creation • Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance. • Diverse & fun office: we believe the hardest problems get solved by the broadest range of minds. We are committed to Equal Employment Opportunity through attracting and retaining a diverse team and building an inclusive environment. • Fractile is seeking to increase the clock speed of global progress, one chip at a time. We’ve recently raised $220M from investors including Founders Fund and Accel and our most important work lies ahead. Join us! • Export controls • Our work involves technologies subject to UK, US and other international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.