Graphcore - Director, Silicon Logical Design

Bristol, UK; Cambridge, UK6mo ago

In Office Director EMEA Semiconductors Architecture Art Director VHDL Team Management Team Leadership Python Documentation

Requirements

• Degree in Computer Science, Electrical Engineering or a related field; advanced degree preferred. • Extensive experience in digital logical design, micro-architecture and RTL development for large scale, high performance silicon projects. • Proven success leading and developing technical teams in a semiconductor environment. • Deep expertise in SystemVerilog or VHDL and familiarity with modern digital design flows. • Strong ability to diagnose and resolve complex design issues, including via scripting/programming (Python, Tcl, etc.). • Demonstrated excellence in cross functional leadership and communication across global teams. • Strong organisational skills with ability to manage multiple priorities and drive execution in fast-paced environments. • Processor or accelerator micro architecture. • High-speed serial interfaces and complex, high bandwidth IP blocks. • Arithmetic pipeline design and floating point datapaths. • Advanced synthesis, timing analysis, power analysis, and logical equivalence checking. • Design-for-test methodologies. • Power integrity and silicon device level understanding. • Experience with silicon bring-up and post-silicon validation. • Program planning and multi-project execution leadership.

Responsibilities

• Leadership & Strategy • Define and execute the strategic roadmap for Logical Design, ensuring alignment with Graphcores silicon and product strategy. • Lead, grow and mentor a high performing RTL/micro architecture design organisation. • Establish and implement best in class design methodologies, documentation standards and quality metrics. • Drive continuous improvement across team structure, workflows, tooling, and design processes. • Technical Ownership • Provide technical oversight of micro architecture specification and RTL development across all major blocks and subsystems. • Guide architectural feasibility studies, contribute to architectural trade offs and micro architecture definition. • Oversee the integration of third party IP, complex application specific blocks, and high performance custom designs. • Ensure robust design sign off through high quality linting, synthesis, CDC/RDC, timing closure and coverage metrics. • Cross-Functional Collaboration • Partner closely with Physical Design, Verification, DFT, Architecture and Program Management teams to ensure cohesive planning and execution. • Foster strong communication across teams and global sites, ensuring alignment on priorities, risks and deliverables. • Support silicon bring-up and debug efforts by providing expert guidance and deep understanding of RTL behaviour and architecture. • Execution & Delivery • Own delivery of high quality, on schedule RTL for multiple parallel silicon programs. • Establish scalable project planning and tracking practices, including resource planning and risk mitigation. • Champion design automation and infrastructure improvements to accelerate productivity and improve design quality.