Fractile - Lead Physical Design Engineer
Requirements
• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field. • 10+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below). • Strong proficiency in EDA tools for place & route, STA, and sign-off. • Solid understanding of CMOS technology, semiconductor physics, and process limitations. • Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures. • Expertise in timing closure, signal integrity, IR drop analysis, and formal verification. • Proficiency in scripting languages like TCL, Perl, or Python for automation. • Excellent problem-solving skills, communication, and teamwork in a collaborative design environment. • Experience in high-performance computing (HPC), AI accelerators, or networking chips. • Founded 2022, we're 100+ people across London and Bristol, in the heart of the UK's frontier AI ecosystem, and growing fast. • We offer competitive salaries, meaningful equity, and standard company benefits. • We believe the hardest problems get solved by the broadest range of minds. We actively encourage applications from underrepresented groups in hardware and software engineering. • Hybrid working; 2-3 days in our London and Bristol offices. • Export controls: • Export controls: • Our work involves technologies subject to UK and international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.
Responsibilities
• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution. • Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics. • Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques. • Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance. • Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation. • Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others. • Interface with foundries and process engineers to ensure manufacturability and yield optimisation. • Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design. • Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Benefits
• Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role. • Equity & Ownership: meaningful equity so everyone shares in the value creation. • Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance. • Diverse & fun office: we believe the hardest problems get solved by the broadest range of minds. We are committed to Equal Employment Opportunity through attracting and retaining a diverse team and building an inclusive environment. • Fractile is seeking to increase the clock speed of global progress, one chip at a time. We’ve recently raised $220M from investors including Founders Fund and Accel and our most important work lies ahead. Join us! • Export controls • Export controls • Our work involves technologies subject to UK, US and other international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.
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