• Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR, PDV and final PD sign off; Own physical design & implementation of high-performance designs from block level to system level components; Deep collaboration with Micro-architects to explore performance, power and area trade-offs for high performance and low power designs; Physical implementation feasibility studies and design recommendations for best PPA develop methodologies and recipes for various stages of physical implementation; Perform various physical design validation PDV) flows for Timing, Power, EM/IR, etc. to ensure physical design quality, Perform design rule checking (DRC), (LVS) checks, and other physical verification tasks.
• IF INTERESTED, PLEASE E-MAIL RESUMES:
• Baya Systems, Inc.:
• Talent Acquisition Manager
• [email protected]