Astera Labs - Senior Analog Mixed-Signal IC Layout Engineer

• Pursuing BS or MS in EE/CS or related fields. • Hardware engineering background with an emphasis in VLSI or Computer Architecture. • Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture. • Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog. • Familiarity with verification methodologies like UVM, functional coverage, assertions. • Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++. • Real-world design and/or verification in Verilog/System Verilog. • Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes. • Familiarity with Synopsys EDA tools. • We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.