Axelera AI - Logical Design Engineer
Requirements
• Education: A degree in electronics engineering, electrical engineering or computer science or other relevant discipline. • Experience: A minimum of 5 years of experience and proven expertise in silicon logical design, with a successful track record in RTL coding and synthesis, digital design, SoC, and integration of 3rd-party IPs (PCIe, LPDDR), with fluency in Verilog. • Expertise: Mastery of industry-standard Electronic Design Automation (EDA) tools for design and verification. Deep understanding of intricate digital design principles, covering clock domain crossing, low-power design, and timing closure. • Scripting: Proficiency in scripting languages such as Python, shell or Tcl for automation. • Collaboration / Team Player: Demonstrated ability to work closely with architecture, verification, physical design and software teams to ensure comprehensive verification coverage. • Problem Solving: Strong analytical and problem-solving skills. • Communication: Excellent written and verbal communication skills in English. Comfortable working with a team spread across 15 countries. • We offer a flexible working arrangement, with options to: • Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom) if you're already based in the vicinity. • Work fully remotely from any European country (incl. the UK) you are already in. • Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven). • This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares. • An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team. • At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.
Responsibilities
• Collaborate with cross-functional teams to clarify and comprehend intricate design specifications and requirements. • Architect and implement advanced micro-architectures from high-level specifications for silicon components, adhering to performance, power, and area (PPA) metrics. • Employ industry-standard design tools and methodologies to fashion and optimize digital logic circuits. • Conduct block and system-level RTL coding, ensuring optimal performance, power, and area (PPA) metrics. • Integrate various IPs/Sub IPs into the top-level SoC. • Perform static checks (lint, cdc, equivalence checks) to enhance the quality of the RTL. • Automate tasks using scripting for efficiency gains. • Undertake comprehensive functional verification and collaborate closely with verification engineers to ensure the correctness of the design. • Actively engage in design reviews, contributing technical expertise to enhance overall design quality. • Work collaboratively with physical design engineers to address design-for-manufacturability (DFM) and design-for-test (DFT) considerations.
Benefits
• Equity options mentioned as part of compensation: "We are creating..." implies potential equity opportunities for employees at Axelera AI to help advance humanity and improve the world around us, suggesting that there may be an opportunity to earn a share in company profits or growth through stock ownership. • Remote work options explicitly stated: "We have built a world-class team of 220+ employees (including...with offices in Belgium, France..." and "...headquartered at the High Tech Campus in Eindhoven, Netherlands." This indicates that remote work is available. • Given these points from the job posting provided:
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