Axelera AI - Senior/Staff Silicon Physical Design Engineer
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Requirements
• 10+ years of experience in Physical Design (RTL to GDS). • Strong communication and teamwork skills. • Expertise in all aspects of physical design. • Hands-on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre). • Proficiency in clocking techniques and CTS. • Experience in IP integration across various domains. • Strong scripting skills (Python and Tcl). • Proven problem-solving and debugging capabilities. • Fluent in English (spoken and written). • Highly preferred: • Highly preferred: • Experience in floorplanning and top level integration. • Knowledge of chip-package-board co-simulation and packaging. • Experience working with EDA vendors to resolve tool issues. • Understanding of semiconductor device physics and multi-domain design. • Location • We offer a flexible working arrangement, with options to: • Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Florence and Milan in Italy or Bristol in the United Kingdom) if you're already based in the vicinity. • Work fully remotely from any European country (incl. the UK) you are already in. • Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven). • Kindly note that priority will be given to candidates who are [interested in being] based in Belgium or Italy. • What we offer • This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares. • An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team. • At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.
Responsibilities
• Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification. • Constraint generation, timing analysis and optimization. • Execute clock tree synthesis (CTS) and custom clock-building techniques. • Integrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs. • Utilize EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre. • Develop automation scripts in Python, Tcl, Bash and contribute to flow development. • Debug and solve technical challenges related to physical design. • Collaborate with architecture, RTL, and verification teams.
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