FortifyIQ - Sr. Hardware Design Engineer

• Strong command of SystemVerilog for RTL design and digital architecture. • Experience using simulation tools such as Questa, Incisive, or VCS. • Skilled in scripting (Python, Perl, Tcl) for automation and workflow optimization. • Proven experience in ASIC or FPGA design, synthesis, and timing closure. • Strong analytical thinking and communication skills, with the ability to manage complex priorities. • 10+ years of relevant experience and a BSEE or MSEE degree. • Preferred / Plus • Preferred / Plus • Expertise in ASIC synthesis, timing constraints, CDC/RDC methodologies. • Familiarity with UVM-based verification environments. • Experience with high-speed memory technologies (HBM, GDDR, LPDDR, DDR). • Understanding of AMBA AXI or CHI protocols.