• BSEE or BSCE with 6+ years of SoC design, verification, or related work experience and 8+ years of experience of FPGA design, bring-up, debugging, and verification.
• In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on an FPGA development platform.
• Solid experience with defining timing constraints for Static Timing Analysis.
• Some familiarity with Cadence SoC design flow.
• Expertise in both Intel Quartus Prime Pro and Xilinx Vivado suites.
• Solid understanding of the tool flow from RTL to bitstream.
• Some familiarity with programming in C language.
• Familiarity with source code control systems (git) required.
• Familiarity with simulation tools.
• Hands-on lab bring-up experience, debug, and instrument usage.
• In addition, the following areas of experience are highly desirable for the position but not strictly required:
• In-depth experience with Stratix 10 FPGA platforms: boards, debug, performance, and throughput tuning.
• In-depth experience with AMD VU19P prototyping systems, debug, design partitioning, performance, and throughput tuning.
• Experience with Siemens proFPGA prototyping/emulation platform and VPS software.
• Experience with ARM’s MPS4 platform.
• Experience with low power designs.
• Experience with embedded microprocessors.
• Proven design validation skills.
• In-depth experience writing Verilog code.
• Experience with System Verilog verification environments.
• Good analytical skills.
• Python script experience.
• Peripheral protocols: I2C, I3C, MSPI, UART, USB