Astera Labs - Senior Physical Design Engineer
Requirements
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field. • 4+ years of experience in physical design with advanced technology nodes (preferably ≤ 5nm). • Strong experience with: • Floor planning, placement, CTS, routing, and IR drop mitigation • Timing closure collaboration with STA team • Hands-on experience with tools such as Synopsys ICC2, Cadence Innovus, Calibre, Voltus. • Experience in integrating high-speed IPs (e.g., SerDes, PHYs) into SoC or chiplet environments. • Experience in high frequence data path, DSP designs. • Solid scripting skills for automation and productivity enhancement. • We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Responsibilities
• Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm. • Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power. • Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis. • Handle advanced physical design topics: • EM/IR analysis and power grid optimization • Congestion analysis and mitigation • Clock domain crossing and skew optimization • RC extraction-aware placement and routing • Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment. • Participate in defining floorplan strategy and chip partitioning for multi-gigabit transceivers. • Perform ECO implementation and support tapeout signoff activities. • Ensure DRC/LVS/ANT/CELL/ERC clean database using industry-standard physical verification tools. • Use industry-standard tools (e.g., ICC2, Innovus, Voltus, RedHawk, Calibre) for implementation and signoff. • Develop and maintain automation scripts (Tcl, Python, Perl) for physical design flows and regressions.
Benefits
• Equity options mentioned: "equity." • Paid PTO/vacation time indicated as part of the benefits package. • Insurance coverage is included in the compensation details provided. • Perks are listed, suggesting additional non-monetary advantages may be available to employees. • Remote work options explicitly stated: "remote work."
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